View ICS9FG107_5005866.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DATASHEET
Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
Description
ICS9FG107 is a Frequency Timing Generator that provides 7 differential output pairs that are compliant to the Intel CK409/CK410 specification. It provides support for PCI-Express, next generation I/ O, and SATA. The part synthesizes several output frequencies from either a 14.31818 Mhz crystal or a 25 MHz crystal. The device can also be driven by a reference input clock instead of a crystal. It provides outputs with cycle-to-cycle jitter of less than 85 ps and output-to-output skew of less than 85 ps. ICS9FG107 also provides a copy of the reference clock and 333 MHz PCI output clocks. Frequency selection can be accomplished via strap pins or SMBus control.
ICS9FG107
Features/Benefits
* * * * * * * * Generates common CPU/PCI Express frequencies from 14.318 MHz or 25 MHz Crystal or reference input 7 - 0.7V current-mode differential output pairs 3 - 33MHz PCI outputs 1 - REFOUT Supports Serial-ATA at 100 MHz Two spread spectrum modes: 0 to -0.5 downspread and +/-0.25% centerspread Unused inputs may be disabled in either driven or Hi-Z state for power management.
Key Specifications
* * * Output cycle-to-cycle jitter for DIF outputs < 50 ps (<85ps @ 266 MHz) Output to output skew for DIF outputs < 85 ps +/-300 ppm frequency accuracy on output clocks
* *
48-pin SSOP/TSSOP package Available in RoHS compliant packaging
Funtional Block Diagram
XIN/CLKIN X2 REFOUT
PCICLK (1:0) SCLK SDATA DIF_STOP# SEL14M_25M# SPREAD DWNSPRD# OE (6:0) FS (2:0) I REF Control Logic Programmable Spread PLL1 Programmable Frequency Dividers PCICLK_F
DIF (6:0) DIF# (6:0)
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
ICS9FG107
REV F 08/21/07
1
ICS9FG107 Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
Pin Configuration
XIN/CLKIN X2 VDD GND FS2/REFOUT* GND FS0/PCICLK_F* PCICLK0 PCICLK1 VDD OE_6** DIF_6 DIF_6# VDD GND OE_5** DIF_5 DIF_5# VDD DIF_4 DIF_4# OE_4* SDATA SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDA GNDA IREF DWNSPRD#* FS1** OE_0* DIF_0 DIF_0# VDD DIF_1 DIF_1# OE_1** VDD GND OE_2** DIF_2 DIF_2# VDD DIF_3 DIF_3# OE_3* SEL14M_25M#** SPREAD* DIF_STOP#
Functionality Table
SEL14M_25M# FS2 FS1 FS0 OUTPUT(MHz) (FS3) 0 0 0 0 100.00 0 0 0 1 125.00 0 0 1 0 133.33 0 0 1 1 166.67 0 1 0 0 200.00 0 1 0 1 266.66 0 1 1 0 333.33 0 1 1 1 400.00 1 0 0 0 100.00 1 0 0 1 125.00 1 0 1 0 133.33 1 0 1 1 166.67 1 1 0 0 200.00 1 1 0 1 266.66 1 1 1 0 333.33 1 1 1 1 400.00
Notes: Pins preceeded by * have 120 Kohm pull UP resistors Pins preceeded by ** have 120 Kohm pull DOWN resistors FS(2:0) and SEL14M_25M# are latched inputs
Power Groups
Pin Number VDD GND 3 4 10 6 14,19,31,36,40 15,35 N/A 47 48 47 Description REFOUT, Digital Inputs, SMBus PCI Outputs DIF Outputs IREF Analog VDD & GND for PLL Core
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
ICS9FG107
ICS9FG107
REV F 08/21/07
2
ICS9FG107 Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
Pin Description
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PIN NAME XIN/CLKIN X2 VDD GND FS2/REFOUT* GND FS0/PCICLK_F* PCICLK0 PCICLK1 VDD OE_6** DIF_6 DIF_6# VDD GND OE_5** DIF_5 DIF_5# VDD DIF_4 DIF_4# OE_4* SDATA SCLK PIN TYPE IN OUT PWR PWR I/O PWR I/O OUT OUT PWR IN OUT OUT PWR PWR IN OUT OUT PWR OUT OUT IN I/O IN DESCRIPTION Crystal input or Reference Clock input Crystal output, Nominally 14.318MHz Power supply, nominal 3.3V Ground pin. Frequency select latch input pin / Reference clock output Ground pin. Frequency select latch input pin / 3.3V PCI free running clock output. PCI clock output. PCI clock output. Power supply, nominal 3.3V Active high input for enabling output 6. 0 = tri-state outputs, 1= enable outputs 0.7V differential true clock output 0.7V differential complement clock output Power supply, nominal 3.3V Ground pin. Active high input for enabling output 5. 0 = tri-state outputs, 1= enable outputs 0.7V differential true clock output 0.7V differential complement clock output Power supply, nominal 3.3V 0.7V differential true clock output 0.7V differential complement clock output Active high input for enabling output 4. 0 = tri-state outputs, 1= enable outputs Data pin for SMBus circuitry, 3.3V tolerant. Clock pin of SMBus circuitry, 5V tolerant.
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
ICS9FG107
REV F 08/21/07
3
ICS9FG107 Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
Pin Description (Continued)
PIN # 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 PIN NAME DIF_STOP# SPREAD* SEL14M_25M#** OE_3* DIF_3# DIF_3 VDD DIF_2# DIF_2 OE_2** GND VDD OE_1** DIF_1# DIF_1 VDD DIF_0# DIF_0 OE_0* FS1** DWNSPRD#* PIN TYPE IN IN IN IN OUT OUT PWR OUT OUT IN PWR PWR IN OUT OUT PWR OUT OUT IN IN IN DESCRIPTION Active low input to stop differential output clocks. Asynchronous, active high input, with internal 120Kohm pull-up resistor, to enable spread spectrum functionality. Select 14.31818 MHz or 25 Mhz input frequency. 1 = 14.31818 MHz, 0 = 25 MHz Active high input for enabling output 3. 0 = tri-state outputs, 1= enable outputs 0.7V differential complement clock output 0.7V differential true clock output Power supply, nominal 3.3V 0.7V differential complement clock output 0.7V differential true clock output Active high input for enabling output 2. 0 = tri-state outputs, 1= enable outputs Ground pin. Power supply, nominal 3.3V Active high input for enabling output 1. 0 = tri-state outputs, 1= enable outputs 0.7V differential complement clock output 0.7V differential true clock output Power supply, nominal 3.3V 0.7V differential complement clock output 0.7V differential true clock output Active high input for enabling output 0. 0 = tri-state outputs, 1= enable outputs 3.3V Frequency select latched input pin. 3.3V input that selects spread mode. This input is not latched at power up. 0 = Down Spread, 1 = Center Spread This pin establishes the reference current for the differential currentmode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin for the PLL core. 3.3V power for the PLL core.
46 47 48
IREF GNDA VDDA
OUT PWR PWR
Pins preceeded by * have 120 Kohm pull UP resistors Pins preceeded by ** have 120 Kohm pull DOWN resistors
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
ICS9FG107
REV F 08/21/07
4
ICS9FG107 Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
General SMBus serial interface information for the ICS9FG107 How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address DC (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address DC (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address DD (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controlle r (Host) starT bit T Slave Address DC(H ) W Rite WR Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Sla ve /Re ce ive r)
Index Block Read Operation
Controlle r (Host) T starT bit Slave Address DC(H ) WR W Rite Beginning Byte = N ACK RT Repeat starT Slave Address DD(H ) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Sla ve /Re ce ive r)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
Byte N + X - 1 N P Not acknowledge stoP bit
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
ICS9FG107
REV F 08/21/07
5
ICS9FG107 Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
I C Table: Device Control Register, READ/WRITE ADDRESS (DC/DD) Byte 0 0 1 Pin # Name Control Function Type 27 RW Bit 7 FS31 5 See Frequency RW Bit 6 FS21 Selection Table, Page 1 44 RW Bit 5 FS11 7 RW Bit 4 FS01 1 26 RW Off On Bit 3 Spread Enable Hardware Software Enable Software Control of Frequency, RW Bit 2 Select Select Spread Enable and Spread Type RW Driven Hi-Z DIF_STOP# drive mode Bit 1 1 RW Down Center 45 Bit 0 DWNSPRD# Notes: 1. These bits reflect the latched state of the corresponding pins at power up, but may be written to if Byte 0, bit 2 is set to '1'. FS3 is the SEL14M_25M# pin. I C Table: Output Enable Register Pin # Name Byte 1 8 PCICLK0 Bit 7 DIF_6 12,13 Bit 6 DIF_5 17,18 Bit 5 DIF_4 20,21 Bit 4 DIF_3 30,29 Bit 3 DIF_2 33,32 Bit 2 DIF_1 39,38 Bit 1 DIF_0 42,41 Bit 0 I C Table: Output Stop Mode Register Pin # Name Byte 2 PCICLK1 9 Bit 7 DIF_6 12,13 Bit 6 DIF_5 17,18 Bit 5 DIF_4 20,21 Bit 4 DIF_3 30,29 Bit 3 DIF_2 33,32 Bit 2 DIF_1 39,38 Bit 1 DIF_0 42,41 Bit 0
2 2
2
PWD Pin 27 Pin 5 Pin 44 Pin 7 Pin 26 0 0 Pin 45
Control Function Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable
Type RW RW RW RW RW RW RW RW
0 Stop Low Disable Disable Disable Disable Disable Disable Disable
1 Enable Enable Enable Enable Enable Enable Enable Enable
PWD 1 1 1 1 1 1 1 1
Control Function Output Enable Stop Mode Stop Mode Stop Mode Stop Mode Stop Mode Stop Mode Stop Mode
Type RW RW RW RW RW RW RW RW
0 Stop Low Free-run Free-run Free-run Free-run Free-run Free-run Free-run
1 Enable Stop-able Stop-able Stop-able Stop-able Stop-able Stop-able Stop-able
PWD 1 0 0 0 0 0 0 0
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
ICS9FG107
REV F 08/21/07
6
ICS9FG107 Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
I C Table: Frequency Select Readback Register Byte 3 Pin # Name Control Function Bit 7 27 SEL14M_25M#1 (FS3) State of pin 27
2
Type R
0
1
PWD Pin 27 Pin 5 Pin 44 Pin 7 Pin 26 X X Pin 45
See Frequency 5 State of pin 6 R Selection Table, Page 1 Bit 6 FS21 44 State of pin 44 R Bit 5 FS11 1 7 State of pin 7 R Bit 4 FS0 26 State of pin 26 R Off On Bit 3 SPREAD1 R RESERVED RESERVED Bit 2 R RESERVED RESERVED Bit 1 45 State of pin 45 R Down Center Bit 0 DWNSPRD1 Notes: 1. These read-only bits always reflect the latched state of the corresponding pins at power up. I C Table: Vendor Byte 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2 2
& Revision ID Register Pin # Name RID3 RID2 RID1 RID0 VID3 VID2 VID1 VID0 -
Control Function REVISION ID
VENDOR ID
Type R R R R R R R R
0 -
1 -
PWD 0 0 0 0 0 0 0 1
I C Table: DEVICE ID Byte 5 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name
Control Function
Device ID = 07 Hex Bit 7 is MSB
Type R R R R R R R R
0
1 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
PWD 0 0 0 0 0 1 1 1
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
ICS9FG107
REV F 08/21/07
7
ICS9FG107 Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
I C Table: Byte Count Register Byte 6 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2
Name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0
Control Function Writing to this register will configure how many bytes will be read back, default is 07 = 7 bytes.
Type RW RW RW RW RW RW RW RW
0 -
1 -
PWD 0 0 0 0 0 1 1 1
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
ICS9FG107
REV F 08/21/07
8
ICS9FG107 Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
DIF_STOP# - Assertion (transition from '1' to '0')
Asserting DIF_STOP# pin stops all DIF outputs that are set to be stoppable after their next transition. When the SMBus DIF_STOP tri-state bit corresponding to the DIF output of interest is programmed to a '0', DIF output will stop DIF_True = HIGH and DIF_Complement = LOW. When the SMBus DIF_STOP tri-state bit corresponding to the DIF output of interest is programmed to a '1', DIFoutputs will be tri-stated.
DIF_STOP# DIF DIF#
DIF_STOP# - De-assertion (transition from '0' to '1')
With the de-assertion of DIF_STOP# all stopped DIF outputs will resume without a glitch. The maximum latency from the de-assertion to active outputs is 2 - 6 DIF clock periods. If the control register tristate bit corresponding to the output of interest is programmed to '1', then the stopped DIF outputs will be driven High within 15nS of DIF_Stop# de-assertion to a voltage greater than 200mV.
DIF_Stop# DIF DIF#
DIF Internal
Tdrive_DIF_Stop, 10nS >200mV
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
ICS9FG107
REV F 08/21/07
9
ICS9FG107 Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
Absolute Max
Symbol VDD_A VDD_In Ts Tambient Tcase ESD prot Parameter 3.3V Core Supply Voltage 3.3V Logic Input Supply Voltage Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection human body model Min GND - 0.5 -65 0 Max VDD + 0.5V VDD + 0.5V 150 70 115 Units V V C C C V
2000
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage V DD = 3.3 V +/-5% PARAMETER Input High Voltage Input Low Voltage Input High Current SYMBOL V IH VIL I IH I IL1 Input Low Current I IL2 CONDITIONS 3.3 V +/-5% 3.3 V +/-5% V IN = VDD V IN = 0 V; Inputs with no pullup resistors VIN = 0 V; Inputs with pull-up resistors Full Active, CL = Full load; f = 400 MHz Full Active, CL = Full load; f = 100 MHz VDD = 3.3 V Logic Inputs Output pin capacitance From VDD Power-Up and after input clock stabilization to 1st clock Triangular Modulation DIF output enable after DIF_Stop# de-assertion 20% to 80% of VDD MIN 2 VSS - 0.3 -5 -5 -200 250 200 14 1.5 25 7 5 6 1.8 30 40 10 5 TYP MAX VDD + 0.3 0.8 5 UNITS NOTES V V uA uA uA mA mA MHz nH pF pF ms kHz ns ns 3 1 1 1 1,2 1 1 1
Operating Supply Current Input Frequency 3 Pin Inductance1 Input/Output Capacitance1 Clk Stabilization1,2 Modulation Frequency DIF output enable Input Rise and Fall times
1 2
I DD3.3OP Fi Lpin CIN COUT TSTAB f MOD t DIFOE t R/t F
Guaranteed by design and characterization, not 100% tested in production. See timing diagrams for timing requirements. 3 Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz or 25 MHz to meet ppm frequency accuracy on PLL outputs.
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
ICS9FG107
REV F 08/21/07
10
ICS9FG107 Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, REF = 475 PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy SYMBOL Zo
1
CONDITIONS VO = Vx
MIN 3000
TYP
MAX
UNITS
NOTES 1 1 1 1 1 1 1 1,2 2 2,3 2 2,3 2 2,3 2 2,3 2 2,3 2 2,3 2 2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1 1 1 1 1 1 1
Statistical measurement on single ended VHigh 660 850 mV signal using oscilloscope math function. VLow -150 150 Measurement on single ended signal using Vovs 1150 mV absolute value. Vuds -300 Vcross(abs) 250 550 mV d-Vcross Variation of crossing over all edges 140 mV ppm see Tperiod min-max values -300 300 ppm 400MHz nominal 2.4993 2.5008 ns 400MHz spread 2.4993 2.5133 ns 333.33MHz nominal 2.9991 3.0009 ns 2.9991 3.016 ns 333.33MHz spread 266.66MHz nominal 3.7489 3.7511 ns 3.7489 3.77 ns 266.66MHz spread 200MHz nominal 4.9985 5.0015 ns Average period Tperiod 200MHz spread 4.9985 5.0266 ns 166.66MHz nominal 5.9982 6.0018 ns 5.9982 6.0320 ns 166.66MHz spread 133.33MHz nominal 7.4978 7.5023 ns 7.4978 5.4000 ns 133.33MHz spread 100.00MHz nominal 9.9970 10.0030 ns 9.9970 10.0533 ns 100.00MHz spread 400MHz nominal/spread 2.4143 ns 2.9141 ns 333.33MHz nominal/spread 3.6639 ns 266.66MHz nominal/spread Tabsmin Absolute min period 4.8735 ns 200MHz nominal/spread 5.8732 ns 166.66MHz nominal/spread 7.3728 ns 133.33MHz nominal/spread 100.00MHz nominal/spread 9.8720 ns VOL = 0.175V, VOH = 0.525V tr 175 700 ps Rise Time VOH = 0.525V VOL = 0.175V tf 175 700 ps Fall Time d-tr Rise Time Variation 125 ps d-tf 125 ps Fall Time Variation dt3 Duty Cycle Measurement from differential wavefrom 45 55 % Measurement from differential wavefrom 50 ps f not equal 266 MHz tjcyc-cyc Jitter, Cycle to cycle Measurement from differential wavefrom 85 ps f = 266 MHz 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz or 25 MHz 3 Figures are for down spread.
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
ICS9FG107
REV F 08/21/07
11
ICS9FG107 Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
Output-Output Skew (DIFF0 as REFERENCE) Window Skew Skew (ps) Dif0:1 Dif0:2 Dif0:3 Dif0:4 Dif0:5 Dif0:6
1
Min 73 Min -52 -48 -46 -52 -73 -72
Mean 54 Mean -28 -25 -25 -26 -52 -54
Max 35 Max -7 -4 -5 -5 -32 -35
NOTES 1
1 1 1 1 1 1
Guaranteed by design and characterization, not 100% tested in production. Output-Output Skew (DIFF3 as REFERENCE) Window Skew Skew (ps) Dif3:0 Dif3:1 Dif3:2 Dif3:4 Dif3:5 Dif3:6 Min 52 Min 2 -25 -24 -22 -50 -49 Mean 53 Mean 23 -5 -2 -2 -29 -30 Max 52 Max 43 18 19 21 -9 -6 1 1 1 1 1 1 NOTES 1
1
Guaranteed by design and characterization, not 100% tested in production.
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
ICS9FG107
REV F 08/21/07
12
ICS9FG107 Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
Electrical Characteristics - PCICLK/PCICLK_F
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP Long Accuracy ppm see Tperiod min-max values -300 33.33MHz output nominal 29.99100 Clock period Tperiod 33.33MHz output spread 29.99100 Absolute Min/Max Clock 33.33MHz output nominal 29.49100 Tabs period 33.33MHz output spread 29.49100 12 Clk High Time th1 12 Clock Low Time t l1 Output High Voltage VOH I OH = -1 mA 2.4 I OL = 1 mA Output Low Voltage VOL V OH @MIN = 1.0 V -33 Output High Current I OH VOH@ MAX = 3.135 V VOL @ MIN = 1.95 V 30 Output Low Current I OL VOL @ MAX = 0.4 V Edge Rate Edge Rate Rise Time Fall Time Duty Cycle Skew Jitter
1 2
MAX 300 30.00900 30.15980 30.50900 30.65980 N/A N/A 0.55 -33 38 4 4 2 2 55 500 250
UNITS ppm ns ns ns ns ns ns V V mA mA mA mA V/ns V/ns ns ns % ps ps
Notes 1,2 2 2 2 2 1 1
t r1 t f1 dt1 t sk1 tjcyc-cyc
Rising edge rate Falling edge rate VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
1 1 0.5 0.5 45
1.4 1.4
1 1 1 1 1 1 1
Guaranteed by design, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz or 25 MHz
Electrical Characteristics - REF-14.318/25 MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) SYMBO CONDITIONS MIN TYP MAX UNITS Notes PARAMETER L Long Accuracy ppm see Tperiod min-max values -300 0 300 ppm 1 14.318MHz output nominal 69.8270 69.8413 69.8550 ns 1,2 Clock period Tperiod 25.000MHz output nominal 39.9880 40.0000 40.0120 ns 1,2 Output High Voltage VOH IOH = -1 mA 2.4 V 1 IOL = 1 mA 0.4 V 1 Output Low Voltage VOL VOH @MIN = 1.0 V, Output High Current IOH -29 -23 mA 1 VOH@MAX = 3.135 V VOL @MIN = 1.95 V, 29 27 mA 1 Output Low Current IOL VOL @MAX = 0.4 V V OL = 0.4 V, V OH = 2.4 V 1 1.6 2 ns 1 Rise Time tr1 V OH = 2.4 V, V OL = 0.4 V 1 1.6 2 ns 1 Fall Time tf1 Duty Cycle Jitter
1 2
dt1 tjcyc-cyc
VT = 1.5 V VT = 1.5 V
45 160
55 250
% ps
1 1
Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818 or 25.00 MHz
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
ICS9FG107
REV F 08/21/07
13
ICS9FG107 Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
SRC Reference Clock Common Recommendations for Differential Routing Dimension or Value L1 length, Route as non-coupled 50 ohm trace. 0.5 max L2 length, Route as non-coupled 50 ohm trace. 0.2 max L3 length, Route as non-coupled 50 ohm trace. 0.2 max Rs 33 Rt 49.9 Down Device Differential Routing L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Differential Routing to PCI Express Connector L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Dimension or Value 2 min to 16 max 1.8 min to 14.4 max Dimension or Value 0.25 to 14 max 0.225 min to 12.6 max
Unit inch inch inch ohm ohm Unit inch inch Unit inch inch
Figure 1 1 1 1 1 Figure 1 1 Figure 2 2
Figure 1 Down device routing.
L1 Rs L1' Rs
L2
L4 L4' Rt L3' Rt L3 PCI Ex Board Down Device REF_CLK Input
L2'
HSCL Output Buffer
Figure 1
Figure 2 PCI Express Connector Routing.
L1 Rs L1' Rs
L2
L4 L4' Rt L3' Rt L3 PCI Ex Add In Board REF_CLK Input
L2'
HSCL Output Buffer
Figure 2
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
ICS9FG107
REV F 08/21/07
14
ICS9FG107 Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
Alternative termination for LVDS and other common differential signals. Figure 3.
Vdiff Vp-p 0.45 v 0.22v 0.58 0.28 0.80 0.40 0.60 0.3 R1a = R1b = R1 Figure_3. Vcm 1.08 0.6 0.6 1.2 R1 33 33 33 33 R2 150 78.7 78.7 174 R3 100 137 none 140 R4 100 100 100 100 Note
ICS874003i-02 input compatible Standard LVDS
L1 R1a L1' R1b
L2
R3
L4 L4'
R4
L2' R2a L3' R2b L3
HSCL Output Buffer
Down Device REF_CLK Input
R2a = R2b = R2
Cable connected AC coupled application, figure 4
Component R5a,R5b R6a,R6b Cc Vcm Value 8.2K 5% 1K 5% 0.1 uF 0.350 volts Note
3.3 Volts
R5a L4 L4'
Cc Cc
R5b
R6a
R6b PCIe Device REF_CLK Input
Figure_4.
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
ICS9FG107
REV F 08/21/07
15
ICS9FG107 Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
N
c
L
E1 INDEX AREA
E
12 h x 45 D
In Millimeters SYMBOL COMMON DIMENSIONS MIN MAX A 2.41 2.80 A1 0.20 0.40 b 0.20 0.34 c 0.13 0.25 D SEE VARIATIONS E 10.03 10.68 E1 7.40 7.60 e 0.635 BASIC h 0.38 0.64 L 0.50 1.02 N SEE VARIATIONS 0 8
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
A A1
N
-C-
48
10-0034
VARIATIONS D mm. MIN MAX 15.75 16.00
D (inch) MIN .620 MAX .630
e
Ref erence Doc.: JEDEC Publicat ion 95, M O-118
b
SEATING PLANE .10 (.004) C
Ordering Information
ICS 9FG107yFLFT
Example:
ICS XXXX y F Lx T
Designation for tape and reel packaging Lead Option (optional) LF = Lead Free LN = Lead Free Annealed Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS = Standard Device
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
ICS9FG107
REV F 08/21/07
16
ICS9FG107 Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
N
c
48-Lead, 6.10 m m . Body, 0.50 m m . Pitch TSSOP (240 m il) (20 m il) In Inches COMMON DIMENSIONS MIN MAX -.047 .002 .006 .032 .041 .007 .011 .0035 .008 SEE VARIATIONS 0.319 BASIC .236 .244 0.020 BASIC .018 .030 SEE VARIATIONS 0 8 -.004
L
SYMBOL A A1 A2 b c D E E1 e L N a aaa VARIATIONS
INDEX AREA
E1
E
12 D
a
In Millimeters COMMON DIMENSIONS MIN MAX -1.20 0.05 0.15 0.80 1.05 0.17 0.27 0.09 0.20 SEE VARIATIONS 8.10 BASIC 6.00 6.20 0.50 BASIC 0.45 0.75 SEE VARIATIONS 0 8 -0.10
A2 A1
A
N 48
D mm. MIN 12.40 MAX 12.60 MIN .488
D (inch) MAX .496
-Ce
b SEATING PLANE
Reference Doc.: JEDEC Publication 95, MO-153
10-0039
aaa C
Ordering Information
ICS 9FG107yGLFT
Example:
ICS XXXX y G Lx T
Designation for tape and reel packaging Lead Option (optional) LF = Lead Free LN = Lead Free Annealed Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS = Standard Device
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
ICS9FG107
REV F 08/21/07
17
ICS9FG107 Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
Revision History
Rev. D E F Issue Date 08/06/07 08/08/07 08/21/07 Description Updated Differential Output Skew Specifications Updated Differential Output Skew Specifications Updated Differential Output Skew Specifications Page # 11 11 11
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015 408-284-8200 Fax: 408-284-2775
For Tech Support
408-284-6578 pcclockhelp@idt.com
Corporate Headquarters
Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.)
Asia Pacific and Japan
Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505
Europe
IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339
TM
(c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA
18

▲Up To Search▲

Price & Availability of ICS9FG107

	To Download ICS9FG107 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .